1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having an SOI (silicon on insulator) structure and a protective circuit for protecting the semiconductor from surge voltages and the like.
2. Description of Related Art
For semiconductor integrated circuit devices, technology for providing a protective circuit for a circuit having a thin-film SOIMOS (silicon on insulator, metal oxide semiconductor) construction is known in the art. FIG. 11 shows one example of a semiconductor integrated circuit device having a protective circuit. In this construction, an N-channel MOSFET (protective transistor) 54 is provided between input pad 51 and ground terminal (V.sub.ss) 52 through protective resistor 53. Here, if a negative surge voltage is applied to input pad 51, N-channel MOSFET 54 switches on, current flows therethrough and thus excess voltage is released and the semiconductor integrated circuit 55 is protected. 0n the other hand, if a positive surge voltage is applied, then due to the construction or the like of the N-channel MOSFET 54, parasitic bipolar operations, avalanche breakdown of the PN junction, punch-through between the source and the drain or the like occurs and leads to the breakdown of the N-channel MOSFET 54 which releases excess electric voltage through the flow of current.
However, the protective transistor (N-channel MOSFET 54) is not as effective with this method of releasing excess voltage by letting current flow via the breakdown of the N-channel MOSFET 54 compared to the case when excess voltage is released using the ON-state of N-channel MOSFET 54. In other words, the protective transistor is less effective when positive surge voltage is applied to it compared to the case when negative surge voltage is applied.
One device proposed to solve this problem is disclosed in FIG. 8 of Japanese Patent Laid Open Publication Hei. 4-226065. This device releases electrostatic charge (excess voltage) provided from the bond pad which is the external input terminal to the ground side. In other words, if negative electrostatic charge is provided from the bond pad, an ESDP (electrostatic discharge protection) diode releases the electrostatic charge; on the other hand, if positive electrostatic charge is provided from the bond pad, the ESDP transistor releases the electrostatic charge.
However, if the ESDP diode and ESDP transistor disclosed in Japanese Patent Laid Open Publication Hei. 4-226065 are formed on the same substrate, an increase in the area of the protective element may be avoided by using a parasitic diode formed between the drain diffusion layer of the ESDP transistor and the semiconductor substrate as the ESDP diode. However, for the transistor having an SOI structure, the parasitic diode is not formed between the above drain diffusion layer and semiconductor substrate and thus there is a need for form the ESDP diode separately. Thus circuit area becomes large during the formation of the ESDP transistor and ESDP diode using an SOI structure.